BibTeX record conf/iccd/Hoover17

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@inproceedings{DBLP:conf/iccd/Hoover17,
  author       = {Steven F. Hoover},
  title        = {Timing-Abstract Circuit Design in Transaction-Level Verilog},
  booktitle    = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
                  Boston, MA, USA, November 5-8, 2017},
  pages        = {525--532},
  publisher    = {{IEEE} Computer Society},
  year         = {2017},
  url          = {https://doi.org/10.1109/ICCD.2017.91},
  doi          = {10.1109/ICCD.2017.91},
  timestamp    = {Thu, 23 Mar 2023 23:59:55 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/Hoover17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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