BibTeX record conf/iccd/ChiangCC07a

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@inproceedings{DBLP:conf/iccd/ChiangCC07a,
  author       = {Ting Wei Chiang and
                  C. Y. Roger Chen and
                  Wei{-}Yu Chen},
  title        = {An efficient gate delay model for {VLSI} design},
  booktitle    = {25th International Conference on Computer Design, {ICCD} 2007, 7-10
                  October 2007, Lake Tahoe, CA, USA, Proceedings},
  pages        = {450--455},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ICCD.2007.4601938},
  doi          = {10.1109/ICCD.2007.4601938},
  timestamp    = {Thu, 23 Mar 2023 23:59:56 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/ChiangCC07a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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