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@inproceedings{DBLP:conf/iccd/ArunachalamDP97,
author = {Ravishankar Arunachalam and
Florentin Dartu and
Lawrence T. Pileggi},
title = {CMOS Gate Delay Models for General RLC Loading},
booktitle = {ICCD},
year = {1997},
pages = {224-229},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Copyright © 2002-01-03 by Michael Ley (ley@uni-trier.de)