Analytical delay models for VLSI interconnects under ramp input.

Andrew B. Kahng Kei Masuko Sudhakar Muddu Analytical delay models for VLSI interconnects under ramp input. 30-36 1996 ICCAD http://doi.acm.org/10.1145/244522.244528 db/conf/iccad/iccad1996.html#KahngMM96