Proposal of a timing model for CMOS logic gates driving a CRC load.

Akio Hirata Hidetoshi Onodera Keikichi Tamaru Proposal of a timing model for CMOS logic gates driving a CRC load. 537-544 1998 ICCAD http://doi.acm.org/10.1145/288548.289083 db/conf/iccad/iccad1998.html#HirataOT98