Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.

Lei Cheng Deming Chen Martin D. F. Wong Mike Hutton Jason Govig Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. 370-375 2007 conf/iccad/2007 ICCAD http://doi.acm.org/10.1145/1326073.1326149 db/conf/iccad/iccad2007.html#ChengCWHG07