A power aware system level interconnect design methodology for latency-insensitive systems.

Vikas Chandra Herman Schmit Anthony Xu Lawrence T. Pileggi A power aware system level interconnect design methodology for latency-insensitive systems. 275-282 2004 conf/iccad/2004 ICCAD http://doi.acm.org/10.1145/1112239.1112288 db/conf/iccad/iccad2004.html#ChandraSXP04