BibTeX record conf/hpsr/KorikawaKHO19

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@inproceedings{DBLP:conf/hpsr/KorikawaKHO19,
  author       = {Tomohiro Korikawa and
                  Akio Kawabata and
                  Fujun He and
                  Eiji Oki},
  title        = {Packet Processing Architecture With Off-Chip {LLC} Using Interleaved
                  3D-Stacked {DRAM}},
  booktitle    = {20th {IEEE} International Conference on High Performance Switching
                  and Routing, {HPSR} 2019, Xi'an, China, May 26-29, 2019},
  pages        = {1--6},
  publisher    = {{IEEE}},
  year         = {2019},
  url          = {https://doi.org/10.1109/HPSR.2019.8807993},
  doi          = {10.1109/HPSR.2019.8807993},
  timestamp    = {Sat, 09 Apr 2022 12:43:49 +0200},
  biburl       = {https://dblp.org/rec/conf/hpsr/KorikawaKHO19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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