BibTeX record conf/hpec/WijeratneKP21

download as .bib file

@inproceedings{DBLP:conf/hpec/WijeratneKP21,
  author       = {Sasindu Wijeratne and
                  Rajgopal Kannan and
                  Viktor K. Prasanna},
  title        = {Reconfigurable Low-latency Memory System for Sparse Matricized Tensor
                  Times Khatri-Rao Product on {FPGA}},
  booktitle    = {2021 {IEEE} High Performance Extreme Computing Conference, {HPEC}
                  2021, Waltham, MA, USA, September 20-24, 2021},
  pages        = {1--7},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/HPEC49654.2021.9622851},
  doi          = {10.1109/HPEC49654.2021.9622851},
  timestamp    = {Mon, 06 Dec 2021 17:33:20 +0100},
  biburl       = {https://dblp.org/rec/conf/hpec/WijeratneKP21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.