Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs.

Koji Inoue Koji Kai Kazuaki Murakami Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. 218-222 1999 HPCA http://computer.org/proceedings/hpca/0004/00040218abs.htm db/conf/hpca/hpca1999.html#InoueKM99