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BibTeX record conf/hotchips/Papazian20
@inproceedings{DBLP:conf/hotchips/Papazian20, author = {Irma Esmer Papazian}, title = {New 3rd Gen Intel\({}^{\mbox{{\textregistered}}}\) Xeon\({}^{\mbox{{\textregistered}}}\) Scalable Processor (Codename: Ice Lake-SP)}, booktitle = {{IEEE} Hot Chips 32 Symposium, {HCS} 2020, Palo Alto, CA, USA, August 16-18, 2020}, pages = {1--22}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/HCS49909.2020.9220434}, doi = {10.1109/HCS49909.2020.9220434}, timestamp = {Tue, 20 Oct 2020 15:28:58 +0200}, biburl = {https://dblp.org/rec/conf/hotchips/Papazian20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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