BibTeX record conf/hipeac/SyrivelisRKP18

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@inproceedings{DBLP:conf/hipeac/SyrivelisRKP18,
  author       = {Dimitris Syrivelis and
                  Andrea Reale and
                  Kostas Katrinis and
                  Christian Pinto},
  editor       = {S{\"{o}}ren Sonntag and
                  Jos{\'{e}} Manuel Garc{\'{\i}}a Carrasco and
                  S{\'{e}}bastien Rumley and
                  Alessandro Cilardo},
  title        = {A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated
                  Computing},
  booktitle    = {Proceedings of the 3rd International Workshop on Advanced Interconnect
                  Solutions and Technologies for Emerging Computing Systems, {AISTECS}
                  2018, Manchester, United Kingdom, January 22-22, 2018},
  pages        = {3:1--3:4},
  publisher    = {{ACM}},
  year         = {2018},
  url          = {https://doi.org/10.1145/3186608.3186611},
  doi          = {10.1145/3186608.3186611},
  timestamp    = {Wed, 21 Nov 2018 12:44:20 +0100},
  biburl       = {https://dblp.org/rec/conf/hipeac/SyrivelisRKP18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}