An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow.

Dominique Borrione Menouer Boubekeur Emil Dumitrescu Marc Renaudin Jean-Baptiste Rigaud Antoine Sirianni An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. 279 2003 HICSS http://computer.org/proceedings/hicss/1874/track9/187490279babs.htm db/conf/hicss/hicss2003-9.html#BorrioneBDRRS03