Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.

J. V. R. Ravindra M. B. Srinivas Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. 111-114 2008 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/1366110.1366138 conf/glvlsi/2008 db/conf/glvlsi/glvlsi2008.html#RavindraS08