<?xml version="1.0"?>
<dblp>
<inproceedings key="conf/glvlsi/RathaJR96" mdate="2004-07-05">
<author>Nalini K. Ratha</author>
<author>Anil K. Jain</author>
<author>Diane T. Rover</author>
<title>FPGA-based high performance page layout segmentation.</title>
<pages>29-34</pages>
<year>1996</year>
<crossref>conf/glvlsi/1996</crossref>
<booktitle>Great Lakes Symposium on VLSI</booktitle>
<ee>http://csdl.computer.org/comp/proceedings/glsvlsi/1996/7502/00/75020029abs.htm</ee>
<url>db/conf/glvlsi/glvlsi1996.html#RathaJR96</url>
</inproceedings>
</dblp>
