Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution.

Gerald G. Lopez Giovanni Fiorenza Thomas J. Bucelot Phillip Restle Mary Yvonne Lanzerotti Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. 38-43 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/1057661.1057672 db/conf/glvlsi/glvlsi2005.html#LopezFBRL05