Low power test generation for path delay faults using stability functions.

Mahilchi Milir Vaseekar Kumar Spyros Tragoudas Low power test generation for path delay faults using stability functions. 8-12 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/1057661.1057666 db/conf/glvlsi/glvlsi2005.html#KumarT05