Frank K. Gürkaynak Andreas Burg Norbert Felber Wolfgang Fichtner D. Gasser F. Hug Hubert Kaeslin A 2 Gb/s balanced AES crypto-chip implementation. 39-44 2004 conf/glvlsi/2004 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/988952.988963 db/conf/glvlsi/glvlsi2004.html#GuurkaynakBFFGHK04