A tool flow for predicting system level timing failures due to interconnect reliability degradation.

Jin Guo Antonis Papanikolaou Michele Stucchi Kristof Croes Zsolt Tokei Francky Catthoor A tool flow for predicting system level timing failures due to interconnect reliability degradation. 291-296 2008 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/1366110.1366180 conf/glvlsi/2008 db/conf/glvlsi/glvlsi2008.html#GuoPSCTC08