Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU.

Joel Grodstein Rachid Rayess Tad Truex Linda Shattuck Sue Lowell Dan Bailey David Bertucci Gabriel P. Bischoff Daniel E. Dever Mike Gowan Roy Lane Brian Lilly Krishna Nagalla Rahul Shah Emily Shriver Shi-Huang Yin Shannon V. Morton Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. 1-6 2002 conf/glvlsi/2002 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/505306.505308 db/conf/glvlsi/glvlsi2002.html#GrodsteinRTSLBBBDGLLNSSYM02