GrodsteinRTSLBBBDGLLNSSYM02'

BibTeX

@inproceedings{DBLP:conf/glvlsi/GrodsteinRTSLBBBDGLLNSSYM02,
  author    = {Joel Grodstein and
               Rachid Rayess and
               Tad Truex and
               Linda Shattuck and
               Sue Lowell and
               Dan Bailey and
               David Bertucci and
               Gabriel P. Bischoff and
               Daniel E. Dever and
               Mike Gowan and
               Roy Lane and
               Brian Lilly and
               Krishna Nagalla and
               Rahul Shah and
               Emily Shriver and
               Shi-Huang Yin and
               Shannon V. Morton},
  title     = {Power and CAD considerations for the 1.75mbyte, 1.2ghz L2
               cache on the alpha 21364 CPU},
  booktitle = {ACM Great Lakes Symposium on VLSI},
  year      = {2002},
  pages     = {1-6},
  ee        = {http://doi.acm.org/10.1145/505306.505308},
  crossref  = {DBLP:conf/glvlsi/2002},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/glvlsi/2002,
  editor    = {Kanad Ghose and
               Patrick H. Madden and
               Vivek De and
               Peter M. Kogge},
  title     = {Proceedings of the 12th ACM Great Lakes Symposium on VLSI
               2002, New York, NY, USA, April 18-19, 2002},
  booktitle = {ACM Great Lakes Symposium on VLSI},
  publisher = {ACM},
  year      = {2002},
  isbn      = {1-58113-462-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}