Rajesh Garg Mario Sanchez Kanupriya Gulati Nikhil Jayakumar Anshul Gupta Sunil P. Khatri A design flow to optimize circuit delay by using standard cells and PLAs. 217-222 2006 conf/glvlsi/2006 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/1127908.1127960 db/conf/glvlsi/glvlsi2006.html#GargSGJGK06