An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512).

Luigi Dadda Marco Macchetti Jeff Owen An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). 421-425 2004 conf/glvlsi/2004 ACM Great Lakes Symposium on VLSI http://doi.acm.org/10.1145/988952.989053 db/conf/glvlsi/glvlsi2004.html#DaddaMO04