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BibTeX record conf/glvlsi/ChenY13
@inproceedings{DBLP:conf/glvlsi/ChenY13, author = {Zhi{-}Wei Chen and Jin{-}Tai Yan}, editor = {Jos{\'{e}} Luis Ayala and Alex K. Jones and Patrick H. Madden and Ayse K. Coskun}, title = {Timing-constrained replacement using spare cells for design changes}, booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris, France, May 2-4, 2013}, pages = {347--348}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2483028.2483136}, doi = {10.1145/2483028.2483136}, timestamp = {Tue, 23 Jul 2019 15:03:09 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ChenY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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