ChenOT96'

BibTeX

@inproceedings{DBLP:conf/glvlsi/ChenOT96,
  author    = {Guangqiu Chen and
               Hidetoshi Onodera and
               Keikichi Tamaru},
  title     = {Timing and Power Optimization by Gate Sizing Considering
               False Paths},
  booktitle = {Great Lakes Symposium on VLSI},
  year      = {1996},
  pages     = {154-},
  ee        = {http://csdl.computer.org/comp/proceedings/glsvlsi/1996/7502/00/75020154abs.htm},
  crossref  = {DBLP:conf/glvlsi/1996},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

@proceedings{DBLP:conf/glvlsi/1996,
  title     = {6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March
               22-23, 1996, Ames, IA, USA},
  booktitle = {Great Lakes Symposium on VLSI},
  publisher = {IEEE Computer Society},
  year      = {1996},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}