A technique for minimizing power during FPGA placement.

Kristofer Vorwerk Madhu Raman Julien Dunoyer Yaun-Chung Hsu Arun Kundu Andrew A. Kennings A technique for minimizing power during FPGA placement. 233-238 2008 FPL http://dx.doi.org/10.1109/FPL.2008.4629937 conf/fpl/2008 db/conf/fpl/fpl2008.html#VorwerkRDHKK08