Riad Stefo Jose Luis Nunez Claudia Feregrino Sudipta Mahapatra Simon Jones FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. 643-647 2001 conf/fpl/2001 FPL http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2147&spage=0643 db/conf/fpl/fpl2001.html#StefoNFMJ01