Power Dissipation Driven FPGA Place and Route Under Delay Constraints.

Kaushik Roy Sharat Prasad Power Dissipation Driven FPGA Place and Route Under Delay Constraints. 57-65 1994 conf/fpl/1994 FPL db/conf/fpl/fpl1994.html#RoyP94 http://dx.doi.org/10.1007/3-540-58419-6_69