A Parallel Pipelined SAT Solver for FPGAs.

M. Redekopp Andreas Dandalis A Parallel Pipelined SAT Solver for FPGAs. 462-468 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=1896&spage=0462 2000 conf/fpl/2000 FPL db/conf/fpl/fpl2000.html#RedekoppD00