Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor.

Martin J. Pearson Chris Melhuish Anthony G. Pipe Mokhtar Nibouche Ian Gilhespy Kevin N. Gurney Benjamin Mitchinson Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. 582-585 2005 conf/fpl/2005 FPL db/conf/fpl/fpl2005.html#PearsonMPNGGM05