Qiang Liu George A. Constantinides Konstantinos Masselos Peter Y. K. Cheung Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. 179-184 2008 FPL http://dx.doi.org/10.1109/FPL.2008.4629928 conf/fpl/2008 db/conf/fpl/fpl2008.html#LiuCMC08