Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.

Tomoya Kitani Yoshifumi Takamoto Isao Naka Keiichi Yasumoto Akio Nakata Teruo Higashino Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. 1145-1148 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2778&spage=1145 2003 conf/fpl/2003 FPL db/conf/fpl/fpl2003.html#KitaniTNYNH03