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BibTeX record conf/fpl/FesquetR05
@inproceedings{DBLP:conf/fpl/FesquetR05, author = {Laurent Fesquet and Marc Renaudin}, editor = {Tero Rissa and Steven J. E. Wilton and Philip Heng Wai Leong}, title = {A Programmable Logic Architecture for Prototyping Clockless Circuits}, booktitle = {Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005}, pages = {293--298}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/FPL.2005.1515737}, doi = {10.1109/FPL.2005.1515737}, timestamp = {Fri, 24 Mar 2023 00:04:51 +0100}, biburl = {https://dblp.org/rec/conf/fpl/FesquetR05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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