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BibTeX record conf/fpl/DuLCSLLY13
@inproceedings{DBLP:conf/fpl/DuLCSLLY13, author = {Fangqing Du and Colin Yu Lin and Xiuhai Cui and Jiabin Sun and Feng Liu and Fei Liu and Haigang Yang}, title = {Timing-constrained minimum area/power {FPGA} memory mapping}, booktitle = {23rd International Conference on Field programmable Logic and Applications, {FPL} 2013, Porto, Portugal, September 2-4, 2013}, pages = {1--4}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPL.2013.6645565}, doi = {10.1109/FPL.2013.6645565}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/DuLCSLLY13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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