Andreas Dandalis Viktor K. Prasanna Bharani Thiruvengadam Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. 315-325 2001 conf/fpl/2001 FPL http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2147&spage=0315 db/conf/fpl/fpl2001.html#DandalisPT01