BibTeX record: conf/fpl/ChengXHH06

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@inproceedings{DBLP:conf/fpl/ChengXHH06,
  author    = {Lerong Cheng and
               Jinjun Xiong and
               Lei He and
               Mike Hutton},
  title     = {{FPGA} Performance Optimization Via Chipwise Placement Considering
               Process Variations},
  booktitle = {Proceedings of the 2006 International Conference on Field Programmable
               Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
  year      = {2006},
  pages     = {1--6},
  crossref  = {DBLP:conf/fpl/2006},
  url       = {http://doi.ieeecomputersociety.org/10.1109/FPL.2006.311193},
  doi       = {10.1109/FPL.2006.311193},
  timestamp = {Fri, 19 Sep 2014 11:55:18 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpl/ChengXHH06},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}
@proceedings{DBLP:conf/fpl/2006,
  title     = {Proceedings of the 2006 International Conference on Field Programmable
               Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
  year      = {2006},
  publisher = {{IEEE}},
  timestamp = {Fri, 19 Sep 2014 11:55:18 +0200},
  biburl    = {http://dblp.uni-trier.de/rec/bib/conf/fpl/2006},
  bibsource = {dblp computer science bibliography, http://dblp.org}
}