Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA.

François Charot Eslam Yahya Charles Wagner Efficient Modular-Pipelined AES Implemenation in Counter Mode on ALTERA FPGA. 282-291 http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2778&spage=282 2003 conf/fpl/2003 FPL db/conf/fpl/fpl2003.html#CharotYW03