A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck.

Claudio Brunelli Fabio Garzia Carmelo Giliberto Jari Nurmi A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. 487-490 2008 FPL http://dx.doi.org/10.1109/FPL.2008.4629990 conf/fpl/2008 db/conf/fpl/fpl2008.html#BrunelliGGN08