An intermediate hardware model with load/store unit for C to FPGA.

Akira Yamawaki Masahiko Iwane An intermediate hardware model with load/store unit for C to FPGA. 279 2009 FPGA http://doi.acm.org/10.1145/1508128.1508184 conf/fpga/2009 db/conf/fpga/fpga2009.html#YamawakiI09