Efficient FPGA implementation of qr decomposition using a systolic array architecture.

Xiaojun Wang Miriam Leeser Efficient FPGA implementation of qr decomposition using a systolic array architecture. 260 2008 FPGA http://doi.acm.org/10.1145/1344671.1344718 conf/fpga/2008 db/conf/fpga/fpga2008.html#WangL08