Clock power reduction for virtex-5 FPGAs.

Qiang Wang Subodh Gupta Jason Helge Anderson Clock power reduction for virtex-5 FPGAs. 13-22 2009 FPGA http://doi.acm.org/10.1145/1508128.1508132 conf/fpga/2009 db/conf/fpga/fpga2009.html#WangGA09