Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.

Paul Teehan Guy G. Lemieux Mark R. Greenstreet Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. 43-52 2009 FPGA http://doi.acm.org/10.1145/1508128.1508136 conf/fpga/2009 db/conf/fpga/fpga2009.html#TeehanLG09