Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.

Ian Kuon Aaron Egier Jonathan Rose Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. 249 2004 conf/fpga/2004 FPGA http://doi.acm.org/10.1145/968280.968327 db/conf/fpga/fpga2004.html#KuonER04