A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract).

David Jefferson Srinivas Reddy Christopher Lane Ninh Ngo Wanli Chang Manuel Mijia Ketan Zaveri Cameron McClintock Richard Cliff A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). 256 1998 FPGA http://doi.acm.org/10.1145/275107.275148 db/conf/fpga/fpga98.html#JeffersonRLNCMZMC98