A 17ps time-to-digital converter implemented in 65nm FPGA technology.

Claudio Favi Edoardo Charbon A 17ps time-to-digital converter implemented in 65nm FPGA technology. 113-120 2009 FPGA http://doi.acm.org/10.1145/1508128.1508145 conf/fpga/2009 db/conf/fpga/fpga2009.html#FaviC09