Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata.

Remy Chevallier Emmanuelle Encrenaz-Tiphène Laurent Fribourg Weiwen Xu Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. 113-127 2006 conf/formats/2006 FORMATS http://dx.doi.org/10.1007/11867340_9 db/conf/formats/formats2006.html#ChevallierEFX06