Verifying VHDL Designs with Multiple Clocks in SMV.

Ales Smrcka Vojtech Rehák Tomás Vojnar David Safránek Petr Matousek Z. Rehák Verifying VHDL Designs with Multiple Clocks in SMV. 148-164 2006 conf/fmics/2006 FMICS/PDMC http://dx.doi.org/10.1007/978-3-540-70952-7_10 db/conf/fmics/fmics2006.html#SmrckaRVSMR06