An FPGA architecture for DRAM-based systolic computations.

Norman Margolus An FPGA architecture for DRAM-based systolic computations. 2-11 1997 conf/fccm/1997 FCCM http://doi.ieeecomputersociety.org/10.1109/FPGA.1997.624599 db/conf/fccm/fccm1997.html#Margolus97