An FPGA implementation of pipelined multiplicative division with IEEE Rounding.

Ronen Goldberg Guy Even Peter-Michael Seidel An FPGA implementation of pipelined multiplicative division with IEEE Rounding. 185-196 2007 FCCM http://dx.doi.org/10.1109/FCCM.2007.59 conf/fccm/2007 db/conf/fccm/fccm2007.html#GoldbergES07