Logic Synthesis and Verification of the CPU and Caches of a Mainframe System.

Huy Nam Nguyen J. P. Tual L. Ducousso M. Thill P. Vallet Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. 60-64 1994 conf/eurodac/1994edac EDAC-ETC-EUROASIC db/conf/eurodac/eurodac1994.html#NguyenTDTV94